Wrong leds lights up in xilinx vivado

by RJ9   Last Updated October 20, 2019 02:25 AM - source

I'm using vivado 2018.3 and nexys4 for hardware. In the constraint file, I wrote

set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { E[4] }];
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { E[3] }];
...

for out puts and

set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { A[0] }];
set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { A[1] }];
...

for the inputs, but when I run the implementation only the LEDs K15 and H17 are lighting up when I flip the switches L16 and J15. Any idea about how to fix this? thanks



Related Questions


vhdl testbench data type confusion

Updated October 08, 2018 15:25 PM

Disabled Options in Xilinx Vivado

Updated July 06, 2017 21:25 PM

Change PL clock

Updated June 26, 2015 14:10 PM

Implementing algorithm on FPGA

Updated April 02, 2019 11:25 AM

How to properly constrain ethernet phy

Updated July 17, 2018 11:25 AM