by Mohamed Hamdy
Last Updated May 15, 2019 16:25 PM - source

I'm new to vhdl and I wanted to make a vco to get 8 different values of frequencies dependent on controlfreq input and I made it successfully but for now I want to add another single bit input so when its value is '1' I divide each frequency of those by 1000 or in other words to get frequency by hertz instead of kilo hertz .. here's my code

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity VCO is
port (
controlfreq: in std_logic_vector(2 downto 0);
clock_out: out std_logic);
end VCO;
architecture bhv of VCO is
signal clk : std_logic;
signal div : std_logic_vector(7 downto 0):=(others=>'0');
begin
process(clk)
begin
if(clk'event and clk='1') then
div <= div + '1';
end if;
end process;
process(clk)
begin
if (controlfreq <= "000") then
clock_out <= div(0);
elsif (controlfreq <= "001") then
clock_out <= div(1);
elsif (controlfreq <= "010") then
clock_out <= div(2);
elsif (controlfreq <= "011") then
clock_out <= div(3);
elsif (controlfreq <= "100") then
clock_out <= div(4);
elsif (controlfreq <= "101") then
clock_out <= div(5);
elsif (controlfreq <= "110") then
clock_out <= div(6);
elsif (controlfreq <= "111") then
clock_out <= div(7);
end if;
end process;
end bhv;
```

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