Is there possibility for a race condition in the following circuit?

by tigrou   Last Updated August 13, 2019 20:25 PM - source

On this wikipedia page, there is an example of a circuit which implements a D latch using NAND gates :

enter image description here Let's say the flip flop is initialized correctly (eg : Q = 0 and !Q = 1).

If D = 1 and E = 0, the right part (which is, AFAIK, a SR latch) will have S = 1 and R = 1 (which will maintain state as expected).

Let's say E goes to 1.

S will become 0. If the gate at the bottom left update at same time, R will be 1 (which is what we want, the SR gate should now output a "1").

However, AFAIK what is likely to happen is that bottom left gate will only update slightly later. Because of that, the right part will have S = 0 and R = 0 for a very short time (which is a forbidden state). Is this correct ?

So to me, there is possibility of a race condition. I might be missing something, that is why I'm I am asking here.

Answers 1

The situation you describe is not a problem, because after that "very short time" the R and S inputs will be valid. It is possible that both of the latch outputs will have the same value for a short period of time, but that is always a possibility during the time when the latch is changing state. However, the final state of the latch is deterministic and not dependent on the gate delays so there is no race condition.

Elliot Alderson
Elliot Alderson
August 13, 2019 18:49 PM

Related Questions

Critical Races in Asynchronous Sequential Circuits

Updated November 10, 2017 13:25 PM

Why does the race hazard theorem work?

Updated October 11, 2016 08:10 AM

How do I avoid race around condition in SR latch?

Updated February 15, 2018 14:25 PM

JK FF Master Slave inner FF race condition

Updated May 03, 2017 09:25 AM